/*
 * Celestica XP Platform Definitions
 *
 * Copyright (c) 2015 Cumulus Networks, Inc.  All rights reserved.
 * Original author: Alan Liebthal <alanl@cumulusnetworks.com>
 * Last modified by: David Yen <dhyen@cumulusnetworks.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 */

#ifndef CEL_XP_PLATFORM_H__
#define CEL_XP_PLATFORM_H__

#define CEL_REDSTONE_XP_NUM_PORTS            (56)
#define CEL_SMALLSTONE_XP_NUM_PORTS          (32)
#define CEL_SEASTONE_NUM_PORTS               (32)

#define CEL_XP_GPIO_1_BASE          (100)
#define CEL_XP_GPIO_1_PIN_COUNT     (40)
#define CEL_XP_GPIO_1_BASE0         (CEL_XP_GPIO_1_BASE)
#define CEL_XP_GPIO_1_BASE1         (CEL_XP_GPIO_1_BASE+8)
#define CEL_XP_GPIO_1_BASE2         (CEL_XP_GPIO_1_BASE1+8)
#define CEL_XP_GPIO_1_BASE3         (CEL_XP_GPIO_1_BASE2+8)
#define CEL_XP_GPIO_1_BASE4         (CEL_XP_GPIO_1_BASE3+8)

#define CEL_XP_GPIO_FAN1_PRESENT    (CEL_XP_GPIO_1_BASE1+2)
#define CEL_XP_GPIO_FAN2_PRESENT    (CEL_XP_GPIO_1_BASE1+3)
#define CEL_XP_GPIO_FAN3_PRESENT    (CEL_XP_GPIO_1_BASE1+4)
#define CEL_XP_GPIO_FAN4_PRESENT    (CEL_XP_GPIO_1_BASE1+5)
#define CEL_XP_GPIO_FAN5_PRESENT    (CEL_XP_GPIO_1_BASE1+6)

#define CEL_XP_GPIO_PWR1_ALERT      (CEL_XP_GPIO_1_BASE2+5)
#define CEL_XP_GPIO_PWR1_ALL_OK     (CEL_XP_GPIO_1_BASE2+6)

#define CEL_XP_GPIO_PWR2_ALERT      (CEL_XP_GPIO_1_BASE3+0)
#define CEL_XP_GPIO_PWR2_ALL_OK     (CEL_XP_GPIO_1_BASE3+1)
#define CEL_XP_GPIO_PWR1_PRESENT    (CEL_XP_GPIO_1_BASE3+3)
#define CEL_XP_GPIO_PWR2_PRESENT    (CEL_XP_GPIO_1_BASE3+4)

#define CEL_XP_GPIO_LED_FAN1_RED    (CEL_XP_GPIO_1_BASE3+5)
#define CEL_XP_GPIO_LED_FAN1_GREEN  (CEL_XP_GPIO_1_BASE3+6)
#define CEL_XP_GPIO_LED_FAN2_RED    (CEL_XP_GPIO_1_BASE3+7)

#define CEL_XP_GPIO_LED_FAN2_GREEN  (CEL_XP_GPIO_1_BASE4+0)
#define CEL_XP_GPIO_LED_FAN3_RED    (CEL_XP_GPIO_1_BASE4+1)
#define CEL_XP_GPIO_LED_FAN3_GREEN  (CEL_XP_GPIO_1_BASE4+2)
#define CEL_XP_GPIO_LED_FAN4_RED    (CEL_XP_GPIO_1_BASE4+3)
#define CEL_XP_GPIO_LED_FAN4_GREEN  (CEL_XP_GPIO_1_BASE4+4)
#define CEL_XP_GPIO_LED_FAN5_RED    (CEL_XP_GPIO_1_BASE4+5)
#define CEL_XP_GPIO_LED_FAN5_GREEN  (CEL_XP_GPIO_1_BASE4+6)

enum {
	RXP_I2C_iSMT_BUS=0,
	RXP_I2C_I801_BUS,
	RXP_I2C_MASTER_SWITCH_BUS=9,
	RXP_I2C_MUX1_BUS0,
	RXP_I2C_MUX1_BUS1,
	RXP_I2C_MUX1_BUS2,
	RXP_I2C_MUX1_BUS3,
	RXP_I2C_MUX1_BUS4,
	RXP_I2C_MUX1_BUS5,
	RXP_I2C_MUX1_BUS6,
	RXP_I2C_MUX1_BUS7,
	RXP_I2C_MUX2_BUS0=20,
	RXP_I2C_MUX2_BUS1,
	RXP_I2C_MUX2_BUS2,
	RXP_I2C_MUX2_BUS3,
	RXP_I2C_MUX2_BUS4,
	RXP_I2C_MUX2_BUS5,
	RXP_I2C_MUX2_BUS6,
	RXP_I2C_MUX2_BUS7,
	RXP_I2C_MUX3_BUS0=30,
	RXP_I2C_MUX3_BUS1,
	RXP_I2C_MUX3_BUS2,
	RXP_I2C_MUX3_BUS3,
	RXP_I2C_MUX3_BUS4,
	RXP_I2C_MUX3_BUS5,
	RXP_I2C_MUX3_BUS6,
	RXP_I2C_MUX3_BUS7,
	RXP_I2C_CPLD_MUX_1=40,
	RXP_I2C_CPLD_MUX_2,
	RXP_I2C_CPLD_MUX_3,
	RXP_I2C_CPLD_MUX_4,
	RXP_I2C_CPLD_MUX_FIRST_PORT=50,
};

#define CPLD_REG_BOARD_TYPE_OFFSET        (0x104)  /* Board Type */
#  define CPLD_BOARD_TYPE_REDXP_VAL       (1)
#  define CPLD_BOARD_TYPE_SMALLXP_VAL     (2)
#  define CPLD_BOARD_TYPE_SEA_VAL         (3)

#endif /* CEL_XP_PLATFORM_H__ */
