/*
 * Dell EMC S41XX CPLD Platform Definitions
 *
 * Copyright (C) 2017 Cumulus Networks, Inc.  All Rights Reserved.
 * David Yen (dhyen@cumulusnetworks.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 */

#ifndef DELL_S41XX_CPLD_H__
#define DELL_S41XX_CPLD_H__

/*------------------------------------------------------------------------------
 *
 * Device data and driver data structures
 *
 * register info from S4148-ON_HW_SPEC_REV09_20151209.pdf
 */
#define CPLD_STRING_NAME_SIZE  30

/* The S4148 actually has three CPLDs: system, master, slave
 * The CPLD driver has been coded such that we have the appearance of a single
 * CPLD. We do this by embedding a two-bit index for which CPLD must be accessed
 * into each register definition. When the register is accessed, the register
 * definition is decoded into a CPLD index and register offset.
 */
#define CPLD_IDX_SHIFT                        (6)
#define SYSTEM_CPLD_ID                        (1)
#define MASTER_CPLD_ID                        (2)
#define SLAVE_CPLD_ID                         (3)
#define CPLD_IDX_MASK                         (3 << CPLD_IDX_SHIFT)
#define SYSTEM_CPLD_IDX                       (SYSTEM_CPLD_ID << CPLD_IDX_SHIFT)
#define MASTER_CPLD_IDX                       (MASTER_CPLD_ID << CPLD_IDX_SHIFT)
#define SLAVE_CPLD_IDX                        (SLAVE_CPLD_ID << CPLD_IDX_SHIFT)
#define NO_S4148_CPLD_I2C_CLIENTS             (3)
#define NO_S4148T_CPLD_I2C_CLIENTS            (2)
#define NO_S4128_CPLD_I2C_CLIENTS             (3)
#define NO_S4128T_CPLD_I2C_CLIENTS            (2)

#define GET_CPLD_IDX(A)           (((A & CPLD_IDX_MASK) >> CPLD_IDX_SHIFT) - 1)
#define STRIP_CPLD_IDX(A)                     (A & ~CPLD_IDX_MASK)

/* The S4148 also has a mux for the QSFP low speed signals. The mux select is
 * controlled by the CPLDs.
 */
#define SFF_MUXES                             (1)
#define SFF_MUX_NUM_PORTS                     (54)
#define SFF_MUX_FIRST_PORT                    (1)
#define FIRST_QSFP_PORT_NUM                   (25)
#define NUM_QSFP_PORTS                        (6)

#define CPLD_SFP_REG_COUNT                    (6)

#define SFF_4128_MUX_NUM_PORTS                (30)
#define NUM_4128_QSFP_PORTS                   (2)
#define CPLD_4128_SFP_REG_COUNT               (4)

/*
 * System CPLD register definitions
 */
#define CPLD_SYS_CPLD_REV_REG                 (0x00 | SYSTEM_CPLD_IDX)
#define  CPLD_SYS_MJR_REV_MASK                (0XF0)
#define  CPLD_SYS_MNR_REV_MASK                (0X0F)

#define CPLD_SYS_CPLD_GPR_REG                 (0x01 | SYSTEM_CPLD_IDX)
#define  CPLD_SYS_SCRTCH_REG_MASK             (0XFF)

#define CPLD_CPU_BRD_REV_TYPE_REG             (0x02 | SYSTEM_CPLD_IDX)
#define  CPLD_CPU_BRD_REV_MASK                (0XF0)
#define  CPLD_CPU_BRD_TYPE_MASK               (0x0F)
#define  CPLD_CPU_BRD_TYPE_NON_NEBS_CPU       (0x00)
#define  CPLD_CPU_BRD_TYPE_NEBS_CPU           (0x01)

#define CPLD_SYS_SRR_REG                      (0x03 | SYSTEM_CPLD_IDX)
#define  CPLD_SYS_SSD_PRESNT_MASK             (0x80)
#define  CPLD_SYS_SPI_CS_SEL_MASK             (0x20)
#define  CPLD_SYS_RST_BIOS_SWITCH_MASK        (0x10)
#define  CPLD_SYS_CPLD_UPGRADE_RST_MASK       (0x02)

#define CPLD_SYS_EEPROM_WP_REG                (0x04 | SYSTEM_CPLD_IDX)
#define  CPLD_SYS_SYSTM_ID_EEPROM_WP_MASK     (0x10)
#define  CPLD_SYS_SPI_WP_GBE_MASK             (0x08)
#define  CPLD_SYS_SPI_BIOS_WP_MASK            (0x04)
#define  CPLD_SYS_SPI_BAK_BIOS_WP_MASK        (0x02)

#define CPLD_SYS_IRQ_REG                      (0x05 | SYSTEM_CPLD_IDX)

#define CPLD_SYS_WD_REG                       (0x06 | SYSTEM_CPLD_IDX)
#define  CPLD_SYS_WD_TIMER_MASK               (0x70)
#define  CPLD_SYS_WD_TIMER_15_SEC             (0x00)
#define  CPLD_SYS_WD_TIMER_20_SEC             (0x10)
#define  CPLD_SYS_WD_TIMER_30_SEC             (0x20)
#define  CPLD_SYS_WD_TIMER_40_SEC             (0x30)
#define  CPLD_SYS_WD_TIMER_50_SEC             (0x40)
#define  CPLD_SYS_WD_TIMER_60_SEC             (0x50)
#define  CPLD_SYS_WD_TIMER_65_SEC             (0x60)
#define  CPLD_SYS_WD_TIMER_70_SEC             (0x70)

#define  CPLD_SYS_WD_EN_MASK                  (0x08)
#define  CPLD_SYS_WD_PUNCH_MASK               (0x01)

#define CPLD_SYS_MB_RST_EN_REG                (0x07 | SYSTEM_CPLD_IDX)
#define  CPLD_SYS_MB_RST_EN_MASK              (0x01)

#define CPLD_SYS_REBOOT_CAUSE_REG             (0x08 | SYSTEM_CPLD_IDX)
#define  CPLD_SYS_COLD_RESET_MASK             (0x80)
#define  CPLD_SYS_WARM_RESET_MASK             (0x40)
#define  CPLD_SYS_THERMAL_SHUTDOWN_MASK       (0x20)
#define  CPLD_SYS_WD_FAIL_MASK                (0x10)
#define  CPLD_SYS_BIOS_SWITCHOVER_MASK        (0x08)
#define  CPLD_SYS_BOOT_FAIL_MASK              (0x04)
#define  CPLD_SYS_SHUT_DOWN_MASK              (0x02)
#define  CPLD_SYS_PWR_ERR_MASK                (0x01)

#define CPLD_SYS_CPU_PWR_EN_STATUS_REG        (0x09 | SYSTEM_CPLD_IDX)
#define  CPLD_SYS_V1P5_EN_MASK                (0x80)
#define  CPLD_SYS_PWR_VDDR_EN_MASK            (0x40)
#define  CPLD_PWR_PWR_CORE_EN_MASK            (0x20)
#define  CPLD_PWR_V1P1_EN_MASK                (0x10)
#define  CPLD_PWR_V1P0_EN_MASK                (0x08)
#define  CPLD_PWR_V3P3_EN_MASK                (0x04)
#define  CPLD_PWR_REG_1V8_EN_MASK             (0x02)
#define  CPLD_PWR_RED_1V35_EN_MASK            (0x01)

#define CPLD_SYS_CPU_PWR_STATUS_REG           (0x0a | SYSTEM_CPLD_IDX)
#define  CPLD_SYS_PG_DDR_VTT_MASK             (0x80)
#define  CPLD_SYS_PG_PVDDR_MASK               (0x40)
#define  CPLD_PWR_PG_PWR_CORE_MASK            (0x20)
#define  CPLD_PWR_PG_V1P1_MASK                (0x10)
#define  CPLD_PWR_PG_V1P0_MASK                (0x08)
#define  CPLD_PWR_PG_3V3_MASK                 (0x04)
#define  CPLD_PWR_PG_1V8_MASK                 (0x02)
#define  CPLD_PWR_PG_1V35_MASK                (0x01)

/*
 * Master CPLD register definitions
 */
#define CPLD_MSTR_CPLD_REV_REG                (0x00 | MASTER_CPLD_IDX)
#define  CPLD_MJR_REV_MASK                    (0XF0)
#define  CPLD_MNR_REV_MASK                    (0x0F)

#define CPLD_MSTR_CPLD_GPR_REG                (0x01 | MASTER_CPLD_IDX)
#define  CPLD_MSTR_SCRTCH_REG_MASK            (0xFF)

#define CPLD_MB_BRD_REV_TYPE_REG              (0x02 | MASTER_CPLD_IDX)
#define  CPLD_MB_BRD_REV_MASK                 (0XF0)
#define  CPLD_MB_BRD_TYPE_MASK                (0x0F)
#define   CPLD_MB_BRD_TYPE_S4148F_NON_NEBS    (0x00)
#define   CPLD_MB_BRD_TYPE_S4148F_NEBS        (0x01)
#define   CPLD_MB_BRD_TYPE_S4128F_NON_NEBS    (0x02)
#define   CPLD_MB_BRD_TYPE_S4128F_NEBS        (0x03)
#define   CPLD_MB_BRD_TYPE_S4148_NON_NEBS     (0x04)
#define   CPLD_MB_BRD_TYPE_S4148_NEBS         (0x05)
#define   CPLD_MB_BRD_TYPE_S4128T_NON_NEBS    (0x06)
#define   CPLD_MB_BRD_TYPE_S4128T_NEBS        (0x07)
#define   CPLD_MB_BRD_TYPE_S4148FE_NON_NEBS   (0x08)
#define   CPLD_MB_BRD_TYPE_S4148FE_NEBS       (0x09)
#define   CPLD_MB_BRD_TYPE_S4148U_NON_NEBS    (0x0C)
#define   CPLD_MB_BRD_TYPE_S4148U_NEBS        (0x0D)

#define CPLD_MSTR_SRR_REG                     (0x03 | MASTER_CPLD_IDX)
#define  CPLD_PORT_LED_RESET_MASK             (0xc0)
#define   CPLD_RESET_LED1_AND_LED2            (0x00)
#define   CPLD_RESET_LED1_ONLY                (0x80)
#define   CPLD_RESET_LED2_ONLY                (0x40)
#define   CPLD_NORMAL_OPERATION               (0xC0)
#define  CPLD_MB_RST_MASK                     (0x20)
#define  CPLD_MICRO_US_RST_MASK               (0x10)
#define  CPLD_1588_RST_MASK                   (0x04)
#define  CPLD_NPU_RST_MASK                    (0x02)
#define  CPLD_MGMT_PHY_RST_MASK               (0x01)

#define CPLD_FAN_EEPROM_WP_REG                (0x04 | MASTER_CPLD_IDX)
#define  CPLD_FAN4_EEPROM_WP_MASK             (0x08)
#define  CPLD_FAN3_EEPROM_WP_MASK             (0x04)
#define  CPLD_FAN2_EEPROM_WP_MASK             (0x02)
#define  CPLD_FAN1_EEPROM_WP_MASK             (0x01)

#define CPLD_MSTR_IRQ_REG                     (0x05 | MASTER_CPLD_IDX)
#define  CPLD_PS2_INT_MASK                    (0x80)
#define  CPLD_PS1_INT_MASK                    (0x40)
#define  CPLD_USB_FAULT_MASK                  (0x20)
#define  CPLD_BCM54616S_INT_MASK              (0x10)
#define  CPLD_1588_MODULE_INT_MASK            (0x08)
#define  CPLD_HOT_SWAP_INT2_MASK              (0x04)
#define  CPLD_HOT_SWAP_INT1_MASK              (0x02)
#define  CPLD_FAN_ALERT_INT_MASK              (0x01)

#define CPLD_SYSTEM_LED_REG                   (0x06 | MASTER_CPLD_IDX)
#define  CPLD_FAN_LED_MASK                    (0xC0)
#define  CPLD_FAN_LED_SHIFT                   (6)
#define  CPLD_FAN_LED_WIDTH                   (2)
#define   CPLD_FAN_LED_OFF                    (0x00)
#define   CPLD_FAN_LED_YELLOW                 (0x40)
#define   CPLD_FAN_LED_GREEN                  (0x80)
#define   CPLD_FAN_LED_YELLOW_BLINKING        (0xC0)
#define  CPLD_SYSTEM_LED_MASK                 (0x30)
#define  CPLD_SYSTEM_LED_SHIFT                (4)
#define  CPLD_SYSTEM_LED_WIDTH                (2)
#define   CPLD_SYSTEM_LED_OFF                 (0x00)
#define   CPLD_SYSTEM_LED_GREEN               (0x10)
#define   CPLD_SYSTEM_LED_YELLOW              (0x20)
#define   CPLD_SYSTEM_LED_YELLOW_BLINKING     (0x30)
#define  CPLD_BEACON_LED_MASK                 (0x08)
#define  CPLD_BEACON_LED_SHIFT                (3)
#define  CPLD_BEACON_LED_WIDTH                (1)
#define   CPLD_BEACON_LED_OFF                 (0x00)
#define   CPLD_BEACON_LED_BLUE_BLINKING       (0x08)
#define  CPLD_POWER_LED_MASK                  (0x06)
#define  CPLD_POWER_LED_SHIFT                 (1)
#define  CPLD_POWER_LED_WIDTH                 (2)
#define   CPLD_POWER_LED_OFF                  (0x00)
#define   CPLD_POWER_LED_YELLOW               (0x02)
#define   CPLD_POWER_LED_GREEN                (0x04)
#define   CPLD_POWER_LED_YELLOW_BLINKING      (0x06)
#define  CPLD_STACK_LED_MASK                  (0x01)
#define  CPLD_STACK_LED_SHIFT                 (0)
#define  CPLD_STACK_LED_WIDTH                 (1)
#define   CPLD_STACK_LED_GREEN                (0x00)
#define   CPLD_STACK_LED_OFF                  (0x01)

#define CPLD_SEVEN_DGT_STACK_LED_REG          (0x07 | MASTER_CPLD_IDX)
#define  CPLD_LED_BLNK_MASK                   (0x40)
#define  CPLD_LED_OFF_MASK                    (0x20)
#define  CPLD_DOT_MASK                        (0x10)
#define  CPLD_DGT_MASK                        (0x0F)
#define   CPLD_NUMBER_0                       (0x00)
#define   CPLD_NUMBER_1                       (0x01)
#define   CPLD_NUMBER_2                       (0x02)
#define   CPLD_NUMBER_3                       (0x03)
#define   CPLD_NUMBER_4                       (0x04)
#define   CPLD_NUMBER_5                       (0x05)
#define   CPLD_NUMBER_6                       (0x06)
#define   CPLD_NUMBER_7                       (0x07)
#define   CPLD_NUMBER_8                       (0x08)
#define   CPLD_NUMBER_9                       (0x09)
#define   CPLD_NUMBER_A                       (0x0A)
#define   CPLD_NUMBER_B                       (0x0B)
#define   CPLD_NUMBER_C                       (0x0C)
#define   CPLD_NUMBER_D                       (0x0D)
#define   CPLD_NUMBER_E                       (0x0E)
#define   CPLD_NUMBER_F                       (0x0F)

#define CPLD_FAN_TRAY_LED_REG                 (0x08 | MASTER_CPLD_IDX)
#define  CPLD_FAN_TRAY4_LED_SHIFT             (6)
#define  CPLD_FAN_TRAY4_LED_WIDTH             (2)
#define  CPLD_FAN_TRAY4_LED_MASK              (0xC0)
#define   CPLD_FAN_TRAY4_LED_OFF              (0x00)
#define   CPLD_FAN_TRAY4_LED_YELLOW           (0x40)
#define   CPLD_FAN_TRAY4_LED_GREEN            (0x80)
#define  CPLD_FAN_TRAY3_LED_SHIFT             (4)
#define  CPLD_FAN_TRAY3_LED_WIDTH             (2)
#define  CPLD_FAN_TRAY3_LED_MASK              (0x30)
#define   CPLD_FAN_TRAY3_LED_OFF              (0x00)
#define   CPLD_FAN_TRAY3_LED_YELLOW           (0x10)
#define   CPLD_FAN_TRAY3_LED_GREEN            (0x20)
#define  CPLD_FAN_TRAY2_LED_SHIFT             (2)
#define  CPLD_FAN_TRAY2_LED_WIDTH             (2)
#define  CPLD_FAN_TRAY2_LED_MASK              (0x0C)
#define   CPLD_FAN_TRAY2_LED_OFF              (0x00)
#define   CPLD_FAN_TRAY2_LED_YELLOW           (0x04)
#define   CPLD_FAN_TRAY2_LED_GREEN            (0x08)
#define  CPLD_FAN_TRAY1_LED_SHIFT             (0)
#define  CPLD_FAN_TRAY1_LED_WIDTH             (2)
#define  CPLD_FAN_TRAY1_LED_MASK              (0x03)
#define   CPLD_FAN_TRAY1_LED_OFF              (0x00)
#define   CPLD_FAN_TRAY1_LED_YELLOW           (0x01)
#define   CPLD_FAN_TRAY1_LED_GREEN            (0x02)

#define CPLD_FAN_TRAY_STATUS_REG              (0x09 | MASTER_CPLD_IDX)
#define  CPLD_FAN_TRAY4_PRESENT_MASK          (0x08)
#define  CPLD_FAN_TRAY3_PRESENT_MASK          (0x04)
#define  CPLD_FAN_TRAY2_PRESENT_MASK          (0x02)
#define  CPLD_FAN_TRAY1_PRESENT_MASK          (0x01)

#define CPLD_MSTR_MISC_CTRL_REG               (0x0A | MASTER_CPLD_IDX)
#define  CPLD_LED_PT_REGEN_MASK               (0x80)
#define  CPLD_LED_TEST_MASK                   (0x60)
#define  CPLD_CPLD_SPI_WP_MASK                (0x10)
#define  CPLD_MICRO_USB_SUSPEND_MASK          (0x08)
#define  CPLD_MSTR_IRQ_EN_MASK                (0x04)
#define  CPLD_MICRO_USB_PRESENT_MASK          (0x02)
#define  CPLD_CNSL_SEL_MASK                   (0x01)

#define CPLD_PSU_EN_STATUS_REG                (0x0B | MASTER_CPLD_IDX)
#define  CPLD_PSU1_PRESENT_L                  (0x80)
#define  CPLD_PSU1_ERROR                      (0x40)
#define  CPLD_PSU1_GOOD                       (0x20)
#define  CPLD_PSU1_ON_L                       (0x10)
#define  CPLD_PSU2_PRESENT_L                  (0x08)
#define  CPLD_PSU2_ERROR                      (0x04)
#define  CPLD_PSU2_GOOD                       (0x02)
#define  CPLD_PSU2_ON_L                       (0x01)

#define CPLD_MB_PWR_EN_STATUS_REG             (0x0C | MASTER_CPLD_IDX)
#define  CPLD_USB1_VBUS_EN_MASK               (0x80)
#define  CPLD_VCC_1V25_EN_MASK                (0x40)
#define  CPLD_HOT_SWAP1_EN_MASK               (0x20)
#define  CPLD_HOT_SWAP2_EN_MASK               (0x10)
#define  CPLD_MAC_AVS1V_EN_MASK               (0x08)
#define  CPLD_MAC1V_EN_MASK                   (0x04)
#define  CPLD_V3P3_EN_MASK                    (0x02)
#define  CPLD_V5P0_EN_MASK                    (0x01)

#define CPLD_MB_PWR_STATUS_REG                (0x0D | MASTER_CPLD_IDX)
#define  CPLD_VCC_3P3_CPLD_MASK               (0x80)
#define  CPLD_VCC_1V25_PG_MASK                (0x40)
#define  CPLD_HOT_SWAP_PG1_MASK               (0x20)
#define  CPLD_HOT_SWAP_PG2_MASK               (0x10)
#define  CPLD_MAC_AVS1V_PG_MASK               (0x08)
#define  CPLD_MAC1V_PG_MASK                   (0x04)
#define  CPLD_VCC3P3_PG_MASK                  (0x02)
#define  CPLD_VCCV5_PG_MASK                   (0x01)

#define CPLD_NPU_ROV_REG                      (0x0E | MASTER_CPLD_IDX)
#define  CPLD_ROV_MASK                        (0x07)
#define   CPLD_AVS_1P0V                       (0x01)
#define   CPLD_AVS_0P95V                      (0x02)
#define   CPLD_AVS_0P90V_BCM56760             (0x04)
#define   CPLD_AVS_1P025V_BCM56768            (0x04)
#define   CPLD_AVS_0P97V_BCM56768             (0x05)

#define CPLD_MB_REBOOT_CAUSE_REG              (0x0F | MASTER_CPLD_IDX)
#define  CPLD_COLD_RESET_MASK                 (0x80)
#define  CPLD_WARM_RESET_MASK                 (0x40)
#define  CPLD_THERMAL_SHUTDOWN_MASK           (0x20)
#define  CPLD_MB_PWR_EN_MASK                  (0x10)
#define  CPLD_FAN_PRESENT_MASK                (0x08)
#define  CPLD_PSU_FAIL_MASK                   (0x04)
#define  CPLD_SHUT_DOWN_MASK                  (0x02)
#define  CPLD_PWR_ERR_MASK                    (0x01)

#define CPLD_PORT_I2C_MUX_REG                 (0x10 | MASTER_CPLD_IDX)
#define  CPLD_PORT_I2C_MUX_MASK               (0x3F)

#define CPLD_IEEE_1588_REG                    (0x11 | MASTER_CPLD_IDX)

#define CPLD_MSTR_IRQ_MSK_REG                 (0x12 | MASTER_CPLD_IDX)

#define CPLD_QSFP_PRESENT_STATUS_REG          (0x18 | MASTER_CPLD_IDX)
#define  CPLD_QSFP30_PRESENT_MASK             (0x20)
#define  CPLD_QSFP29_PRESENT_MASK             (0x10)
#define  CPLD_QSFP28_PRESENT_MASK             (0x08)
#define  CPLD_QSFP27_PRESENT_MASK             (0x04)
#define  CPLD_QSFP26_PRESENT_MASK             (0x02)
#define  CPLD_QSFP25_PRESENT_MASK             (0x01)

#define CPLD_QSFP_RST_REG                     (0x19 | MASTER_CPLD_IDX)
#define  CPLD_PORT30_RST_MASK                 (0x20)
#define  CPLD_PORT29_RST_MASK                 (0x10)
#define  CPLD_PORT28_RST_MASK                 (0x08)
#define  CPLD_PORT27_RST_MASK                 (0x04)
#define  CPLD_PORT26_RST_MASK                 (0x02)
#define  CPLD_PORT25_RST_MASK                 (0x01)

#define CPLD_QSFP_MODSEL_REG                  (0x1A | MASTER_CPLD_IDX)
#define  CPLD_PORT30_MODSEL_MASK              (0x20)
#define  CPLD_PORT29_MODSEL_MASK              (0x10)
#define  CPLD_PORT28_MODSEL_MASK              (0x08)
#define  CPLD_PORT27_MODSEL_MASK              (0x04)
#define  CPLD_PORT26_MODSEL_MASK              (0x02)
#define  CPLD_PORT25_MODSEL_MASK              (0x01)

#define CPLD_QSFP_LPMODE_REG                  (0x1B | MASTER_CPLD_IDX)
#define  CPLD_PORT30_LPMODE_MASK              (0x20)
#define  CPLD_PORT29_LPMODE_MASK              (0x10)
#define  CPLD_PORT28_LPMODE_MASK              (0x08)
#define  CPLD_PORT27_LPMODE_MASK              (0x04)
#define  CPLD_PORT26_LPMODE_MASK              (0x02)
#define  CPLD_PORT25_LPMODE_MASK              (0x01)

#define CPLD_QSFP_IRQ_STATUS_REG              (0x1C | MASTER_CPLD_IDX)
#define  CPLD_PORT30_IRQ_STATUS_MASK          (0x20)
#define  CPLD_PORT29_IRQ_STATUS_MASK          (0x10)
#define  CPLD_PORT28_IRQ_STATUS_MASK          (0x08)
#define  CPLD_PORT27_IRQ_STATUS_MASK          (0x04)
#define  CPLD_PORT26_IRQ_STATUS_MASK          (0x02)
#define  CPLD_PORT25_IRQ_STATUS_MASK          (0x01)

#define CPLD_QSFP_IRQ_MSK_REG                 (0x1D | MASTER_CPLD_IDX)
#define  CPLD_PORT30_IRQ_MSK_MASK             (0x20)
#define  CPLD_PORT29_IRQ_MSK_MASK             (0x10)
#define  CPLD_PORT28_IRQ_MSK_MASK             (0x08)
#define  CPLD_PORT27_IRQ_MSK_MASK             (0x04)
#define  CPLD_PORT26_IRQ_MSK_MASK             (0x02)
#define  CPLD_PORT25_IRQ_MSK_MASK             (0x01)

#define CPLD_PORT_8_1_PRESENT_STATUS_REG      (0x20 | MASTER_CPLD_IDX)
#define CPLD_PORT_16_9_PRESENT_STATUS_REG     (0x21 | MASTER_CPLD_IDX)
#define CPLD_PORT_8_1_TX_DISABLE_REG          (0x22 | MASTER_CPLD_IDX)
#define CPLD_PORT_16_9_TX_DISABLE_REG         (0x23 | MASTER_CPLD_IDX)
#define CPLD_PORT_8_1_RX_LOS_STATUS_REG       (0x24 | MASTER_CPLD_IDX)
#define CPLD_PORT_16_9_RX_LOS_STATUS_REG      (0x25 | MASTER_CPLD_IDX)
#define CPLD_PORT_8_1_TX_FAULT_STATUS_REG     (0x26 | MASTER_CPLD_IDX)
#define CPLD_PORT_16_9_TX_FAULT_STATUS_REG    (0x27 | MASTER_CPLD_IDX)

#define CPLD_PHY_8_1_RST_REG                  (0x28 | MASTER_CPLD_IDX)
#define CPLD_PHY_8_1_RST_WIDTH                (8)
#define CPLD_PHY_8_1_RST_MASK                 (0xFF)
#define  CPLD_PHY_8_RST_MASK                  (0x80)
#define  CPLD_PHY_7_RST_MASK                  (0x40)
#define  CPLD_PHY_6_RST_MASK                  (0x20)
#define  CPLD_PHY_5_RST_MASK                  (0x10)
#define  CPLD_PHY_4_RST_MASK                  (0x08)
#define  CPLD_PHY_3_RST_MASK                  (0x04)
#define  CPLD_PHY_2_RST_MASK                  (0x02)
#define  CPLD_PHY_1_RST_MASK                  (0x01)

#define CPLD_PHY_12_9_RST_REG                 (0x29 | MASTER_CPLD_IDX)
#define CPLD_PHY_12_9_RST_WIDTH               (8)
#define CPLD_PHY_12_9_RST_MASK                (0x0F)
#define  CPLD_PHY_12_RST_MASK                 (0x08)
#define  CPLD_PHY_11_RST_MASK                 (0x04)
#define  CPLD_PHY_10_RST_MASK                 (0x02)
#define  CPLD_PHY_9_RST_MASK                  (0x01)

/*
 * Slave CPLD register definitions
 */
#define CPLD_SLV_CPLD_REV_REG                 (0x00 | SLAVE_CPLD_IDX)

#define CPLD_SLV_CPLD_GPR_REG                 (0x01 | SLAVE_CPLD_IDX)

/*
 *  This is really how the datasheet explains these register offsets.  No joke.
 *
 *  Note: ports 25-30 are QSFP so they don't show up here.
 *
 *  PORT_[j+8*(i+1)-1]_[j+8*i]_PRESENT_STATUS offset=0x10+i*1
 *      0<=i<=3, j=17+k where k=0 when i=0 else 6
 *
 *  If my math is correct that, expands to:
 *
 *  i=0: (k=0,j=17): [17+8*(0+1)-1]-[17+8*0] offset=0x10+0
 *                    24:17 offset 0x10
 *  i=1: (k=6,j=23): [23+8*(1+1)-1]-[23+8*1] offset=0x10+1
 *                    38:31 offset 0x11
 *  i=2: (k=6,j=23): [23+8*(2+1)-1]-[23+8*2] offset=0x10+2
 *                    46:39 offset 0x12
 *  i=3: (k=6,j=23): [23+8*(3+1)-1]-[23+8*3] offset=0x10+3
 *                    54:47 offset 0x13
 */
#define CPLD_PORT_24_17_PRESENT_STATUS_REG    (0x10 | SLAVE_CPLD_IDX)
/* 25-30 are QSFP */
#define CPLD_PORT_38_31_PRESENT_STATUS_REG    (0x11 | SLAVE_CPLD_IDX)
#define CPLD_PORT_46_39_PRESENT_STATUS_REG    (0x12 | SLAVE_CPLD_IDX)
#define CPLD_PORT_54_47_PRESENT_STATUS_REG    (0x13 | SLAVE_CPLD_IDX)

#define CPLD_PORT_24_17_TX_DISABLE_REG        (0x14 | SLAVE_CPLD_IDX)
/* 25-30 are QSFP */
#define CPLD_PORT_38_31_TX_DISABLE_REG        (0x15 | SLAVE_CPLD_IDX)
#define CPLD_PORT_46_39_TX_DISABLE_REG        (0x16 | SLAVE_CPLD_IDX)
#define CPLD_PORT_54_47_TX_DISABLE_REG        (0x17 | SLAVE_CPLD_IDX)

#define CPLD_PORT_24_17_RX_LOS_STATUS_REG     (0x18 | SLAVE_CPLD_IDX)
/* 25-30 are QSFP */
#define CPLD_PORT_38_31_RX_LOS_STATUS_REG     (0x19 | SLAVE_CPLD_IDX)
#define CPLD_PORT_46_39_RX_LOS_STATUS_REG     (0x1A | SLAVE_CPLD_IDX)
#define CPLD_PORT_54_47_RX_LOS_STATUS_REG     (0x1B | SLAVE_CPLD_IDX)

#define CPLD_PORT_24_17_TX_FAULT_STATUS_REG   (0x1C | SLAVE_CPLD_IDX)
/* 25-30 are QSFP */
#define CPLD_PORT_38_31_TX_FAULT_STATUS_REG   (0x1D | SLAVE_CPLD_IDX)
#define CPLD_PORT_46_39_TX_FAULT_STATUS_REG   (0x1E | SLAVE_CPLD_IDX)
#define CPLD_PORT_54_47_TX_FAULT_STATUS_REG   (0x1F | SLAVE_CPLD_IDX)

/* S4128 only */
#define CPLD_PORT_34_27_PRESENT_STATUS_REG    (0x11 | SLAVE_CPLD_IDX)
#define CPLD_PORT_34_27_TX_DISABLE_REG        (0x15 | SLAVE_CPLD_IDX)
#define CPLD_PORT_34_27_RX_LOS_STATUS_REG     (0x19 | SLAVE_CPLD_IDX)
#define CPLD_PORT_34_27_TX_FAULT_STATUS_REG   (0x1D | SLAVE_CPLD_IDX)

#endif  /* DELL_S41XX_CPLD_H__ */
