/*
 * Celestica Redstone CPLD Platform Definitions
 *
 * Curt Brune <curt@cumulusnetworks.com>
 * Vidya Ravipati <vidya@cumulusnetworks.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 */

#ifndef CEL_REDSTONE_H__
#define CEL_REDSTONE_H__

/*----------------------------------------------------------------------------------
 *
 * register info from R0697-M0010-01 Rev0.2 Redstone D2020 Assembly Spec 05022013.pdf
 */

#define CPLD1_REG_VERSION_OFFSET		(0x00)
#  define CPLD1_VERSION_H_MASK			(0xF0)
#  define CPLD1_VERSION_H_SHIFT         (4)
#    define CPLD1_VERSION_ID			(0x10)
#  define CPLD1_VERSION_L_MASK          (0x0F)
#  define CPLD1_VERSION_L_SHIFT         (0)

#define CPLD1_REG_PLAT_TYPE_OFFSET		(0x02)
#  define CPLD1_PLAT_HW_MASK			(0xE0)
#    define CPLD1_PLAT_CELESTICA		(0x00)
#    define CPLD1_PLAT_DCN				(0x20)
#    define CPLD1_PLAT_TENCENT			(0x40)
#    define CPLD1_PLAT_JUNIPER			(0x60)
#  define CPLD1_PLAT_BOARD_ID_MASK		(0x0C)
#    define CPLD1_PLAT_BOARD_84757		(0x00)
#    define CPLD1_PLAT_BOARD_84754		(0x04)
#    define CPLD1_PLAT_BOARD_NONE       (0x08)
#  define CPLD1_PLAT_BOARD_VER_MASK		(0x03)

#define CPLD1_REG_SW_SCRATCH_OFFSET		(0x04)

#define CPLD1_REG_SYS_BOOT_OK_OFFSET	(0x0A)
#  define CPLD1_SYS_UBOOT_OK_MASK		(0x78)
#    define CPLD1_SYS_UBOOT_OK			(0x50)

#define CPLD1_REG_RESET_CTRL_OFFSET		(0x10)	/* all resets active low */
#  define CPLD1_FLASH_NOR_WRITE_OK		(1 << 3)
#  define CPLD1_RESET_WATCH_DOG_MASK	(1 << 2) /* Watchdog Reset */
#  define CPLD1_RESET_CPU_HARD_L		(1 << 1) /* SW HARD Reset */
#  define CPLD1_RESET_CPU_SOFT_L		(1 << 0) /* SW Soft Reset */

#define CPLD1_REG_RESET_SRC_OFFSET		(0x12) /* Reset Source */
#  define CPLD1_REG_RESET_SRC_MASK		(0x0F)
#    define CPLD1_RESET_PWR_ON			(1 << 3) /* Power On Reset */
#    define CPLD1_RESET_WATCH_DOG		(1 << 2) /* Watchdog Reset */
#    define CPLD1_RESET_CPU_HARD		(1 << 1) /* SW-set hard Reset */
#    define CPLD1_RESET_CPU_SOFT		(1 << 0) /* CPU request Reset */

#define CPLD1_REG_RESET_CTRL_1_OFFSET	(0x14)	/* all resets active low */
#  define CPLD1_RESET_DDR3_L			(1 << 6)
#  define CPLD1_RESET_NOR_FLASH_L		(1 << 5)
#  define CPLD2_RESET_L					(1 << 4)
#  define CPLD3_RESET_L					(1 << 3)
#  define CPLD1_RESET_USB_PHY_L			(1 << 2)
#  define CPLD1_RESET_BCM54616S_L		(1 << 1) /* Front panel mgmt PHY */
#  define CPLD_RESET_BCM56846_L			(1 << 0) /* Trident PHY */

#define CPLD1_REG_RESET_CTRL_2_OFFSET	(0x16)	/* all resets active low */
#  define CPLD1_RESET_CPLD_4_L          (1 << 4)
#  define CPLD1_RESET_EYE_OPEN_4_L		(1 << 3)
#  define CPLD1_RESET_EYE_OPEN_3_L		(1 << 2)
#  define CPLD1_RESET_EYE_OPEN_2_L		(1 << 1)
#  define CPLD1_RESET_EYE_OPEN_1_L		(1 << 0)

#define CPLD1_REG_INT_STATUS_OFFSET		(0x18)
#  define CPLD1_INT_FRU_L			    (1 << 6) /* EMC2305,BCM54616S,NCP4200-Alert */
                                                 /* NCP4200-Fault,ROV-Alert,ROV_Fault */
#  define CPLD1_INT_THERMAL_L			(1 << 5) /* THERMAL_INT1_N~THERMAL_INT5_N */
#  define CPLD1_INT_CPLD_RTC_L          (1 << 4) /* CPLD RTC_INTA & CPLD_RTC_INTB */
#  define CPLD1_INT_PSU_L				(1 << 3) /* PSU_R_ALERT & PSU_L_ALERT */
#  define CPLD1_INT_CPLD_1_4_MOD_ABS	(1 << 2) /* CPLD MOD ABS status for 1-4 */
#  define CPLD1_INT_CPLD_1_4_RX_LOS     (1 << 1) /* CPLD RX LOS status for 1-4 */

#define CPLD1_REG1_INT1_SRC_STATUS_OFFSET	(0x22)
#  define CPLD1_INT_CPLD4_RX_LOS_L		(1 << 2)
#  define CPLD1_INT_CPLD3_RX_LOS_L		(1 << 1)
#  define CPLD1_INT_CPLD2_RX_LOS_L		(1 << 0)

#define CPLD1_REG1_INT2_SRC_STATUS_OFFSET	(0x26)
#  define CPLD1_INT_CPLD4_MOD_ABS_L			(1 << 2)
#  define CPLD1_INT_CPLD3_MOD_ABS_L			(1 << 1)
#  define CPLD1_INT_CPLD2_MOD_ABS_L			(1 << 0)

#define CPLD1_REG_INT3_SRC_STATUS_OFFSET	(0x2A)
#  define CPLD1_INT_PSU_L_L		(1 << 1)
#  define CPLD1_INT_PSU_R_L		(1 << 0)

#define CPLD1_REG_INT4_SRC_STATUS_OFFSET	(0x2C)
#  define CPLD1_INT_RTC_B_L		(1 << 1)
#  define CPLD1_INT_RTC_A_L		(1 << 0)

#define CPLD1_REG_INT5_SRC_STATUS_OFFSET	(0x2E)
#  define CPLD1_INT_THERMAL_SENSOR_6_L		(1 << 5)
#  define CPLD1_INT_THERMAL_SENSOR_5_L		(1 << 4)
#  define CPLD1_INT_THERMAL_SENSOR_4_L		(1 << 3)
#  define CPLD1_INT_THERMAL_SENSOR_3_L		(1 << 2)
#  define CPLD1_INT_THERMAL_SENSOR_2_L		(1 << 1)
#  define CPLD1_INT_THERMAL_SENSOR_1_L		(1 << 0)

#define CPLD1_REG1_INT6_SRC_STATUS_OFFSET	(0x30)
#  define CPLD1_INT_EMC2305_L				(1 << 5)
#  define CPLD1_INT_BCM54616S_L				(1 << 4)
#  define CPLD1_INT_NCP4200_ALERT_L			(1 << 3)
#  define CPLD1_INT_NCP4200_FAULT_L			(1 << 2)
#  define CPLD1_INT_NCP4200_ROV_ALERT_L		(1 << 1)
#  define CPLD1_INT_NCP4200_ROV_FAULT_L		(1 << 0)

#define CPLD1_REG1_INT1_SRC_CHANGE_OFFSET	(0x42)
#  define CPLD1_INT_CHANGE_CPLD4_RX_LOS		(1 << 2)
#  define CPLD1_INT_CHANGE_CPLD3_RX_LOS		(1 << 1)
#  define CPLD1_INT_CHANGE_CPLD2_RX_LOS		(1 << 0)

#define CPLD1_REG1_INT2_SRC_CHANGE_OFFSET	(0x46)
#  define CPLD1_INT_CHANGE_CPLD4_MOD_ABS	(1 << 2)
#  define CPLD1_INT_CHANGE_CPLD3_MOD_ABS	(1 << 1)
#  define CPLD1_INT_CHANGE_CPLD2_MOD_ABS	(1 << 0)

#define CPLD1_REG_INT3_SRC_CHANGE_OFFSET	(0x4A)
#  define CPLD1_INT_CHANGE_PSU_L	(1 << 1)
#  define CPLD1_INT_CHANGE_PSU_R	(1 << 0)

#define CPLD1_REG_INT4_SRC_CHANGE_OFFSET	(0x4C)
#  define CPLD1_INT_CHANGE_RTC_B		(1 << 1)
#  define CPLD1_INT_CHANGE_RTC_A		(1 << 0)

#define CPLD1_REG_INT5_SRC_CHANGE_OFFSET	(0x4E)
#  define CPLD1_INT_CHANGE_THERMAL_SENSOR_6		(1 << 5)
#  define CPLD1_INT_CHANGE_THERMAL_SENSOR_5		(1 << 4)
#  define CPLD1_INT_CHANGE_THERMAL_SENSOR_4		(1 << 3)
#  define CPLD1_INT_CHANGE_THERMAL_SENSOR_3		(1 << 2)
#  define CPLD1_INT_CHANGE_THERMAL_SENSOR_2		(1 << 1)
#  define CPLD1_INT_CHANGE_THERMAL_SENSOR_1		(1 << 0)


#define CPLD1_REG1_INT6_SRC_CHANGE_OFFSET	(0x50)
#  define CPLD1_INT_CHANGE_EMC2305			(1 << 5)
#  define CPLD1_INT_CHANGE_BCM54616S		(1 << 4)
#  define CPLD1_INT_CHANGE_NCP4200_ALERT	(1 << 3)
#  define CPLD1_INT_CHANGE_NCP4200_FAULT	(1 << 2)
#  define CPLD1_INT_CHANGE_NCP4200_ROV_ALERT (1 << 1)
#  define CPLD1_INT_CHANGE_NCP4200_ROV_FAULT (1 << 0)

#define CPLD1_REG1_INT1_SRC_MASK_OFFSET		(0x62)
#  define CPLD1_INT_MASK_CPLD4_RX_LOS		(1 << 2)
#  define CPLD1_INT_MASK_CPLD3_RX_LOS		(1 << 1)
#  define CPLD1_INT_MASK_CPLD2_RX_LOS		(1 << 0)

#define CPLD1_REG1_INT2_SRC_MASK_OFFSET		(0x66)
#  define CPLD1_INT_MASK_CPLD4_MOD_ABS	(1 << 2)
#  define CPLD1_INT_MASK_CPLD3_MOD_ABS	(1 << 1)
#  define CPLD1_INT_MASK_CPLD2_MOD_ABS	(1 << 0)

#define CPLD1_REG_INT3_SRC_MASK_OFFSET	(0x6A)
#  define CPLD1_INT_MASK_PSU_L		(1 << 1)
#  define CPLD1_INT_MASK_PSU_R		(1 << 0)

#define CPLD1_REG_INT4_SRC_MASK_OFFSET	(0x6C)
#  define CPLD1_INT_MASK_RTC_B		(1 << 1)
#  define CPLD1_INT_MASK_RTC_A		(1 << 0)

#define CPLD1_REG_INT5_SRC_MASK_OFFSET	(0x6E)
#  define CPLD1_INT_MASK_THERMAL_SENSOR_6		(1 << 5)
#  define CPLD1_INT_MASK_THERMAL_SENSOR_5		(1 << 4)
#  define CPLD1_INT_MASK_THERMAL_SENSOR_4		(1 << 3)
#  define CPLD1_INT_MASK_THERMAL_SENSOR_3		(1 << 2)
#  define CPLD1_INT_MASK_THERMAL_SENSOR_2		(1 << 1)
#  define CPLD1_INT_MASK_THERMAL_SENSOR_1		(1 << 0)

#define CPLD1_REG1_INT6_SRC_MASK_OFFSET	(0x70)
#  define CPLD1_INT_MASK_EMC2305			(1 << 5)
#  define CPLD1_INT_MASK_BCM54616S			(1 << 4)
#  define CPLD1_INT_MASK_NCP4200_ALERT		(1 << 3)
#  define CPLD1_INT_MASK_NCP4200_FAULT		(1 << 2)
#  define CPLD1_INT_MASK_NCP4200_ROV_ALERT	(1 << 1)
#  define CPLD1_INT_MASK_NCP4200_ROV_FAULT	(1 << 0)

#define CPLD1_REG_PSU_STATUS		(0x80)
#  define CPLD1_PSU_1_MASK			(0x2A)
#    define CPLD1_PSU_1_PRESENT_L	(1 << 5)
#    define CPLD1_PSU_1_OK			(1 << 3)
#    define CPLD1_PSU_1_ON			(1 << 1)
#  define CPLD1_PSU_2_MASK			(0x15)
#    define CPLD1_PSU_2_PRESENT_L	(1 << 4)
#    define CPLD1_PSU_2_OK			(1 << 2)
#    define CPLD1_PSU_2_ON			(1 << 0)

#define CPLD1_REG_FAN_PRESENT_STATUS_OFFSET	(0x90)
#  define CPLD1_FAN_PRESENT_MASK		(0x1F)
#    define CPLD1_FAN_5_PRESENT_L		(1 << 4)
#    define CPLD1_FAN_4_PRESENT_L		(1 << 3)
#    define CPLD1_FAN_3_PRESENT_L		(1 << 2)
#    define CPLD1_FAN_2_PRESENT_L		(1 << 1)
#    define CPLD1_FAN_1_PRESENT_L		(1 << 0)

#define CPLD1_REG_SYS_LED_CTRL_OFFSET       (0x98)
#  define CPLD1_SYS_LED_MASK				(0x03)
#    define CPLD1_SYS_LED_GREEN				(0x00)
#    define CPLD1_SYS_LED_GREEN_SLOW_BLINK	(0x01)
#    define CPLD1_SYS_LED_GREEN_FAST_BLINK	(0x02)
#    define CPLD1_SYS_LED_OFF				(0x03)

/* CPLD_2 and CPLD_3 Register Mapping */
#define CPLD2_REG_VERSION_OFFSET		(0x00)
#  define CPLD2_VERSION_H_MASK			(0xF0)
#  define CPLD2_VERSION_H_SHIFT         (4)
#    define CPLD2_VERSION_ID			(0x20)
#  define CPLD2_VERSION_L_MASK          (0x0F)
#  define CPLD2_VERSION_L_SHIFT         (0)

#define CPLD2_REG_SW_SCRATCH_OFFSET	(0x02)

#define CPLD3_REG_VERSION_OFFSET	(0x04)
#  define CPLD3_VERSION_H_MASK		(0xF0)
#  define CPLD3_VERSION_H_SHIFT		(4)
#  	 define CPLD3_VERSION_ID		(0x30)
#  define CPLD3_VERSION_L_MASK      (0x0F)
#  define CPLD3_VERSION_L_SHIFT     (0)

#define CPLD3_REG_SW_SCRATCH_OFFSET	(0x06)

#define CPLD2_REG_PORT_LED_CLEAR_OFFSET	(0x08)
/* Make sure to set the bit to 0 for 56846 control*/
#  define CPLD2_LED_CLEAR_SFPP_1_18		(1 << 0)

#define CPLD3_REG_PORT_LED_CLEAR_OFFSET	(0x0A)
/* Make sure to set the bit to 0 for 56846 control*/
#  define CPLD3_LED_CLEAR_SFPP_19_36	(1 << 0)

#define CPLD2_REG_I2C_PORT_ID_OFFSET	(0x10)
#  define CPLD2_I2C_BAUD_RATE			(1 << 6) /* 0 - 50KHz, 1 - 100KHz */
#  define CPLD2_I2C_OPCODE_ID_MASK		(0x1F)

#define CPLD2_REG_I2C_OPCODE_OFFSET		(0x12)
#  define CPLD2_I2C_DATA_LEN_MASK		(0xF0)
#  define CPLD2_I2C_DATA_LEN_SHIFT		(4)
#  define CPLD2_I2C_CMD_LEN_MASK		(0x03)
#    define CPLD2_I2C_CMD_CUR_ADDR		(0x00)

#define CPLD2_REG_DEV_ADDR_OFFSET		(0x14)
#  define CPLD2_I2C_SLAVE_ADDR_MASK		(0xFE)
#  define CPLD2_I2C_CMD_INDICATOR_MASK	(0x01)
#    define CPLD2_I2C_CMD_WRITE_OP		(0x00)
#    define CPLD2_I2C_CMD_READ_OP		(0x01)

#define CPLD2_REG_I2C_CMD_BYTE0_OFFSET	(0x18)

/* Byte 1 & 2 not used in Redstone */
#define CPLD2_REG_I2C_CMD_BYTE1_OFFSET	(0x1A)
#define CPLD2_REG_I2C_CMD_BYTE2_OFFSET	(0x1C)

#define CPLD2_REG_I2C_STATUS_SW_RESET_OFFSET	(0x1E)
#  define CPLD2_I2C_MASTER_ERR			(1 << 7)
#  define CPLD2_I2C_BUSY_INDICATOR		(1 << 6)
#  define CPLD2_I2C_MASTER_SOFT_RESET_L	(1 << 0)


/* I2C Write data Byte 0-7 Register */
#define CPLD2_REG_I2C_WRITE_DATA_BYTE0_OFFSET	(0x20)
#define CPLD2_REG_I2C_WRITE_DATA_BYTE1_OFFSET	(0x22)
#define CPLD2_REG_I2C_WRITE_DATA_BYTE2_OFFSET	(0x24)
#define CPLD2_REG_I2C_WRITE_DATA_BYTE3_OFFSET	(0x26)
#define CPLD2_REG_I2C_WRITE_DATA_BYTE4_OFFSET	(0x28)
#define CPLD2_REG_I2C_WRITE_DATA_BYTE5_OFFSET	(0x2A)
#define CPLD2_REG_I2C_WRITE_DATA_BYTE6_OFFSET	(0x2C)
#define CPLD2_REG_I2C_WRITE_DATA_BYTE7_OFFSET	(0x2E)

/* I2C Write data Byte 0-7 Register */
#define CPLD2_REG_I2C_READ_DATA_BYTE0_OFFSET	(0x30)
#define CPLD2_REG_I2C_READ_DATA_BYTE1_OFFSET	(0x32)
#define CPLD2_REG_I2C_READ_DATA_BYTE2_OFFSET	(0x34)
#define CPLD2_REG_I2C_READ_DATA_BYTE3_OFFSET	(0x36)
#define CPLD2_REG_I2C_READ_DATA_BYTE4_OFFSET	(0x38)
#define CPLD2_REG_I2C_READ_DATA_BYTE5_OFFSET	(0x3A)
#define CPLD2_REG_I2C_READ_DATA_BYTE6_OFFSET	(0x3C)
#define CPLD2_REG_I2C_READ_DATA_BYTE7_OFFSET	(0x3E)

#define CPLD3_REG_I2C_PORT_ID_OFFSET	(0x40)
#  define CPLD3_I2C_BAUD_RATE			(1 << 6) /* 0 - 50KHz, 1 - 100KHz */
#  define CPLD3_I2C_OPCODE_ID_MASK		(0x1F)

#define CPLD3_REG_I2C_OPCODE_OFFSET		(0x42)
#  define CPLD3_I2C_DATA_LEN_MASK		(0xF0)
#  define CPLD3_I2C_DATA_LEN_SHIFT		(4)
#  define CPLD3_I2C_CMD_LEN_MASK		(0x03)
#    define CPLD3_I2C_CMD_CUR_ADDR		(0x00)

#define CPLD3_REG_DEV_ADDR_OFFSET		(0x44)
#  define CPLD3_I2C_SLAVE_ADDR_MASK		(0xFE)
#  define CPLD3_I2C_CMD_INDICATOR_MASK	(0x01)
#    define CPLD3_I2C_CMD_WRITE_OP		(0x00)
#    define CPLD3_I2C_CMD_READ_OP		(0x01)

#define CPLD3_REG_I2C_CMD_BYTE0_OFFSET	(0x48)

/* Byte 1 & 2 not used in Redstone */
#define CPLD3_REG_I2C_CMD_BYTE1_OFFSET	(0x4A)
#define CPLD3_REG_I2C_CMD_BYTE2_OFFSET	(0x4C)

#define CPLD3_REG_I2C_STATUS_SW_RESET_OFFSET	(0x4E)
#  define CPLD3_I2C_MASTER_ERR			(1 << 7)
#  define CPLD3_I2C_BUSY_INDICATOR		(1 << 6)
#  define CPLD3_I2C_MASTER_SOFT_RESET_L	(1 << 0)

/* I2C Write data Byte 0-7 Register */
#define CPLD3_REG_I2C_WRITE_DATA_BYTE0_OFFSET	(0x50)
#define CPLD3_REG_I2C_WRITE_DATA_BYTE1_OFFSET	(0x52)
#define CPLD3_REG_I2C_WRITE_DATA_BYTE2_OFFSET	(0x54)
#define CPLD3_REG_I2C_WRITE_DATA_BYTE3_OFFSET	(0x56)
#define CPLD3_REG_I2C_WRITE_DATA_BYTE4_OFFSET	(0x58)
#define CPLD3_REG_I2C_WRITE_DATA_BYTE5_OFFSET	(0x5A)
#define CPLD3_REG_I2C_WRITE_DATA_BYTE6_OFFSET	(0x5C)
#define CPLD3_REG_I2C_WRITE_DATA_BYTE7_OFFSET	(0x5E)

/* I2C Write data Byte 0-7 Register */
#define CPLD3_REG_I2C_READ_DATA_BYTE0_OFFSET	(0x60)
#define CPLD3_REG_I2C_READ_DATA_BYTE1_OFFSET	(0x62)
#define CPLD3_REG_I2C_READ_DATA_BYTE2_OFFSET	(0x64)
#define CPLD3_REG_I2C_READ_DATA_BYTE3_OFFSET	(0x66)
#define CPLD3_REG_I2C_READ_DATA_BYTE4_OFFSET	(0x68)
#define CPLD3_REG_I2C_READ_DATA_BYTE5_OFFSET	(0x6A)
#define CPLD3_REG_I2C_READ_DATA_BYTE6_OFFSET	(0x6C)
#define CPLD3_REG_I2C_READ_DATA_BYTE7_OFFSET	(0x6E)

/* CPLD_4 Register Mapping */
#define CPLD4_REG_VERSION_OFFSET		(0x70)
#  define CPLD4_VERSION_H_MASK			(0xF0)
#  define CPLD4_VERSION_H_SHIFT         (4)
#    define CPLD4_VERSION_ID			(0x20)
#  define CPLD4_VERSION_L_MASK          (0x0F)
#  define CPLD4_VERSION_L_SHIFT         (0)

#define CPLD4_REG_SW_SCRATCH_OFFSET	(0x72)

#define CPLD4_REG_PORT_LED_CLEAR_OFFSET	(0x74)
/* Make sure to set the bit to 0 for 56846 control*/
#  define CPLD_LED_CLEAR_SFPP_37_48_QSFP (1 << 0)

#define CPLD4_REG_I2C_PORT_ID_OFFSET	(0x80)
#  define CPLD4_I2C_BAUD_RATE			(1 << 6) /* 0 - 50KHz, 1 - 100KHz */
#  define CPLD4_I2C_OPCODE_ID_MASK		(0x1F)

#define CPLD4_REG_I2C_OPCODE_OFFSET		(0x82)
#  define CPLD4_I2C_DATA_LEN_MASK		(0xF0)
#  define CPLD4_I2C_DATA_LEN_SHIFT		(4)
#  define CPLD4_I2C_CMD_LEN_MASK		(0x03)
#    define CPLD4_I2C_CMD_CUR_ADDR		(0x00)

#define CPLD4_REG_DEV_ADDR_OFFSET		(0x84)
#  define CPLD4_I2C_SLAVE_ADDR_MASK		(0xFE)
#  define CPLD4_I2C_CMD_INDICATOR_MASK	(0x01)
#    define CPLD4_I2C_CMD_WRITE_OP		(0x00)
#    define CPLD4_I2C_CMD_READ_OP		(0x01)

#define CPLD4_REG_I2C_CMD_BYTE0_OFFSET	(0x88)

/* Byte 1 & 2 not used in Redstone */
#define CPLD4_REG_I2C_CMD_BYTE1_OFFSET	(0x8A)
#define CPLD4_REG_I2C_CMD_BYTE2_OFFSET	(0x8C)

#define CPLD4_REG_I2C_STATUS_SW_RESET_OFFSET	(0x8E)
#  define CPLD4_I2C_MASTER_ERR			(1 << 7)
#  define CPLD4_I2C_BUSY_INDICATOR		(1 << 6)
#  define CPLD4_I2C_MASTER_SOFT_RESET_L	(1 << 0)


/* I2C Write data Byte 0-7 Register */
#define CPLD4_REG_I2C_WRITE_DATA_BYTE0_OFFSET	(0x90)
#define CPLD4_REG_I2C_WRITE_DATA_BYTE1_OFFSET	(0x92)
#define CPLD4_REG_I2C_WRITE_DATA_BYTE2_OFFSET	(0x94)
#define CPLD4_REG_I2C_WRITE_DATA_BYTE3_OFFSET	(0x96)
#define CPLD4_REG_I2C_WRITE_DATA_BYTE4_OFFSET	(0x98)
#define CPLD4_REG_I2C_WRITE_DATA_BYTE5_OFFSET	(0x9A)
#define CPLD4_REG_I2C_WRITE_DATA_BYTE6_OFFSET	(0x9C)
#define CPLD4_REG_I2C_WRITE_DATA_BYTE7_OFFSET	(0x9E)

/* I2C Write data Byte 0-7 Register */
#define CPLD4_REG_I2C_READ_DATA_BYTE0_OFFSET	(0xA0)
#define CPLD4_REG_I2C_READ_DATA_BYTE1_OFFSET	(0xA2)
#define CPLD4_REG_I2C_READ_DATA_BYTE2_OFFSET	(0xA4)
#define CPLD4_REG_I2C_READ_DATA_BYTE3_OFFSET	(0xA6)
#define CPLD4_REG_I2C_READ_DATA_BYTE4_OFFSET	(0xA8)
#define CPLD4_REG_I2C_READ_DATA_BYTE5_OFFSET	(0xAA)
#define CPLD4_REG_I2C_READ_DATA_BYTE6_OFFSET	(0xAC)
#define CPLD4_REG_I2C_READ_DATA_BYTE7_OFFSET	(0xAE)

#define CPLD_REG_SFPP_1_OFFSET	(0xB0)
#define CPLD_REG_SFPP_3_OFFSET	(0xB2)
#define CPLD_REG_SFPP_5_OFFSET	(0xB4)
#define CPLD_REG_SFPP_7_OFFSET	(0xB6)
#define CPLD_REG_SFPP_9_OFFSET	(0xB8)
#define CPLD_REG_SFPP_11_OFFSET	(0xBA)
#define CPLD_REG_SFPP_13_OFFSET	(0xBC)
#define CPLD_REG_SFPP_15_OFFSET	(0xBE)
#define CPLD_REG_SFPP_17_OFFSET	(0xC0)
#define CPLD_REG_SFPP_19_OFFSET	(0xC2)
#define CPLD_REG_SFPP_21_OFFSET	(0xC4)
#define CPLD_REG_SFPP_23_OFFSET	(0xC6)
#define CPLD_REG_SFPP_25_OFFSET	(0xC8)
#define CPLD_REG_SFPP_27_OFFSET	(0xCA)
#define CPLD_REG_SFPP_29_OFFSET	(0xCC)
#define CPLD_REG_SFPP_31_OFFSET	(0xCE)
#define CPLD_REG_SFPP_33_OFFSET	(0xD0)
#define CPLD_REG_SFPP_35_OFFSET	(0xD2)
#define CPLD_REG_SFPP_37_OFFSET	(0xD4)
#define CPLD_REG_SFPP_39_OFFSET	(0xD6)
#define CPLD_REG_SFPP_41_OFFSET	(0xD8)
#define CPLD_REG_SFPP_43_OFFSET	(0xDA)
#define CPLD_REG_SFPP_45_OFFSET	(0xDC)
#define CPLD_REG_SFPP_47_OFFSET	(0xDE)
#  define CPLD_SFPP_2_SPEED_RS		(1 << 7)
#  define CPLD_SFPP_2_PRESENT_L		(1 << 6) /* 0-Present, 1-Absent */
#  define CPLD_SFPP_2_TX_FAIL		(1 << 5)
#  define CPLD_SFPP_2_TX_DISABLE	(1 << 4)
#  define CPLD_SFPP_1_SPEED_RS		(1 << 3)
#  define CPLD_SFPP_1_PRESENT_L		(1 << 2) /* 0-Present, 1-Absent */
#  define CPLD_SFPP_1_TX_FAIL		(1 << 1)
#  define CPLD_SFPP_1_TX_DISABLE	(1 << 0)


#define CPLD_REG_QSFP_1_OFFSET	(0xE0)
#define CPLD_REG_QSFP_2_OFFSET	(0xE2)
#define CPLD_REG_QSFP_3_OFFSET	(0xE4)
#define CPLD_REG_QSFP_4_OFFSET	(0xE6)
#  define CPLD_QSFPP_I2C_READY		(1 << 4) /* 0-I2C Ready, 1-I2C Not Ready */
#  define CPLD_QSFPP_INT_STATUS_L	(1 << 3) /* 0-Interrupt, 1-Not Interrupt */
#  define CPLD_QSFPP_PRESENT_L		(1 << 2) /* 0-Present  , 1-Absent */
#  define CPLD_QSFPP_LPMOD_L		(1 << 1) /* 0-Normal   , 1-Low Power */
#  define CPLD_QSFPP_RESET_L		(1 << 0) /* 0-Reset    , 1-Enable */

#define CPLD2_QSFPP_RESET_L1    (0x70) /* qsfp[1-8] reset, active low */
#define CPLD2_QSFPP_RESET_L2    (0x72) /* qsfp[9-16] reset, active low */
#define CPLD2_QSFPP_LPMOD_L1    (0x74) /* qsfp[1-8] lpmod, active low */
#define CPLD2_QSFPP_LPMOD_L2    (0x76) /* qsfp[9-16] lpmod, active low */
#define CPLD2_QSFPP_PRESENT_L1  (0x84) /* qsfp[1-8] present, active low */
#define CPLD2_QSFPP_PRESENT_L2  (0x86) /* qsfp[9-16] present, active low */

#define CPLD2_QSFPP_RESET_L3    (0xa0) /* qsfp[17-24] reset, active low */
#define CPLD2_QSFPP_RESET_L4    (0xa2) /* qsfp[25-32] reset, active low */
#define CPLD2_QSFPP_LPMOD_L3    (0xa4) /* qsfp[17-24] lpmod, active low */
#define CPLD2_QSFPP_LPMOD_L4    (0xa6) /* qsfp[25-32] lpmod, active low */
#define CPLD2_QSFPP_PRESENT_L3  (0xc4) /* qsfp[17-24] present, active low */
#define CPLD2_QSFPP_PRESENT_L4  (0xc6) /* qsfp[25-32] present, active low */

#endif /* CEL_REDSTONE_H__ */
