/*
 * delta-ag9032v2 CPLD Platform Definitions
 *
 * Copyright (C) 2018 Cumulus Networks, Inc.  All Rights Reserved.
 * Author: David Yen (dhyen@cumulusnetworks.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 */

#ifndef DELTA_AG9032V2_CPLD_H__
#define DELTA_AG9032V2_CPLD_H__

/*
 * The DELTA-AG9032V2 has two CPU accessible CPLDs: system and master. A 2-bit
 * index for selecting the CPLD is encoded into each register definition.  When
 * a register is accessed, the register definition is automatically decoded
 * into a CPLD index a register offset, making the two CPLDs appear as a single
 * CPLD.
 */
#define CPLD_IDX_SHIFT         (6)
#define SYSTEM_CPLD_ID         (1)
#define MASTER_CPLD_ID         (2)
#define CPLD_IDX_MASK          (3 << CPLD_IDX_SHIFT)
#define SYSTEM_CPLD_IDX        (SYSTEM_CPLD_ID << CPLD_IDX_SHIFT)
#define MASTER_CPLD_IDX        (MASTER_CPLD_ID << CPLD_IDX_SHIFT)
#define NUM_CPLDS              (2)

#define GET_CPLD_IDX(A)        (((A & CPLD_IDX_MASK) >> CPLD_IDX_SHIFT) - 1)
#define STRIP_CPLD_IDX(A)      (A & ~CPLD_IDX_MASK)

#define NAME_SIZE              (30)

/* System CPLD registers */
#define SYSTEM_CPLD_SYS_CPLD_REV_REG                (0x00 | SYSTEM_CPLD_IDX)
#define   SYSTEM_CPLD_MJR_REV_MASK                  (0xf0)
#define   SYSTEM_CPLD_MNR_REV_MASK                  (0x0f)

#define SYSTEM_CPLD_CPU_BRD_REV_REG                 (0x02 | SYSTEM_CPLD_IDX)
#define   SYSTEM_CPLD_BRD_REV_MASK                  (0xf0)
#define   SYSTEM_CPLD_BRD_TYPE_MASK                 (0x0f)

#define SYSTEM_CPLD_SYS_EEPROM_WP_REG               (0x04 | SYSTEM_CPLD_IDX)
#define   SYSTEM_CPLD_SYSTEM_ID_EEPROM_WP_MASK      (0x10)

/* Master CPLD registers */
#define MASTER_CPLD_HW_REVISION_REG                 (0x01 | MASTER_CPLD_IDX)
#define   MASTER_CPLD_PLATFORM_TYPE_MASK            (0x0f)

#define MASTER_CPLD_SW_RESET_REG                    (0x02 | MASTER_CPLD_IDX)
#define   MASTER_CPLD_RESET_N_B56870_MASK           BIT(1)

#define MASTER_CPLD_PSU_STATUS_REG                  (0x03 | MASTER_CPLD_IDX)
#define   MASTER_CPLD_PS1_PRESENT_N_MASK            BIT(7)
#define   MASTER_CPLD_PS1_PWR_FAN_OK_MASK           BIT(6)
#define   MASTER_CPLD_PS1_PSON_N_MASK               BIT(4)
#define   MASTER_CPLD_PS2_PRESENT_N_MASK            BIT(3)
#define   MASTER_CPLD_PS2_PWR_FAN_OK_MASK           BIT(2)
#define   MASTER_CPLD_PS2_PSON_N_MASKASK            BIT(0)

#define MASTER_CPLD_QSFP28_MODSEL_1_8_REG           (0x0a | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_MODSEL_9_16_REG          (0x0b | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_MODSEL_17_24_REG         (0x0c | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_MODSEL_25_32_REG         (0x0d | MASTER_CPLD_IDX)

#define MASTER_CPLD_QSFP28_LPMODE_1_8_REG           (0x0e | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_LPMODE_9_16_REG          (0x0f | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_LPMODE_17_24_REG         (0x10 | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_LPMODE_25_32_REG         (0x11 | MASTER_CPLD_IDX)

#define MASTER_CPLD_QSFP28_PRESENT_1_8_REG          (0x12 | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_PRESENT_9_16_REG         (0x13 | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_PRESENT_17_24_REG        (0x14 | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_PRESENT_25_32_REG        (0x15 | MASTER_CPLD_IDX)

#define MASTER_CPLD_QSFP28_RESETN_1_8_REG           (0x16 | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_RESETN_9_16_REG          (0x17 | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_RESETN_17_24_REG         (0x18 | MASTER_CPLD_IDX)
#define MASTER_CPLD_QSFP28_RESETN_25_32_REG         (0x19 | MASTER_CPLD_IDX)

#define MASTER_CPLD_FAN_2_5_LED_REG                 (0x20 | MASTER_CPLD_IDX)
#define   MASTER_CPLD_FAN5_LED_MASK                 (0xc0)
#define   MASTER_CPLD_FAN5_LED_OFF                  (0x00)
#define   MASTER_CPLD_FAN5_LED_GREEN                (0x40)
#define   MASTER_CPLD_FAN5_LED_RED                  (0x80)
#define   MASTER_CPLD_FAN4_LED_MASK                 (0x30)
#define   MASTER_CPLD_FAN4_LED_OFF                  (0x00)
#define   MASTER_CPLD_FAN4_LED_GREEN                (0x10)
#define   MASTER_CPLD_FAN4_LED_RED                  (0x20)
#define   MASTER_CPLD_FAN3_LED_MASK                 (0x0c)
#define   MASTER_CPLD_FAN3_LED_OFF                  (0x00)
#define   MASTER_CPLD_FAN3_LED_GREEN                (0x04)
#define   MASTER_CPLD_FAN3_LED_RED                  (0x08)
#define   MASTER_CPLD_FAN2_LED_MASK                 (0x03)
#define   MASTER_CPLD_FAN2_LED_OFF                  (0x00)
#define   MASTER_CPLD_FAN2_LED_GREEN                (0x01)
#define   MASTER_CPLD_FAN2_LED_RED                  (0x02)

#define MASTER_CPLD_FAN_1_LED_REG                   (0x23 | MASTER_CPLD_IDX)
#define   MASTER_CPLD_FAN1_LED_MASK                 (0xc0)
#define   MASTER_CPLD_FAN1_LED_OFF                  (0x00)
#define   MASTER_CPLD_FAN1_LED_GREEN                (0x40)
#define   MASTER_CPLD_FAN1_LED_RED                  (0x80)

#define MASTER_CPLD_SYSTEM_LED_REG                  (0x21 | MASTER_CPLD_IDX)
#define   MASTER_CPLD_PSU1_LED_MASK                 (0xc0)
#define   MASTER_CPLD_PSU1_LED_OFF                  (0x00)
#define   MASTER_CPLD_PSU1_LED_GREEN                (0x40)
#define   MASTER_CPLD_PSU1_LED_RED                  (0x80)
#define   MASTER_CPLD_PSU2_LED_MASK                 (0x30)
#define   MASTER_CPLD_PSU2_LED_OFF                  (0x00)
#define   MASTER_CPLD_PSU2_LED_GREEN                (0x10)
#define   MASTER_CPLD_PSU2_LED_RED                  (0x20)
#define   MASTER_CPLD_SYS_LED_MASK                  (0x0c)
#define   MASTER_CPLD_SYS_LED_OFF                   (0x00)
#define   MASTER_CPLD_SYS_LED_GREEN                 (0x04)
#define   MASTER_CPLD_SYS_LED_GREEN_BLINKING        (0x08)
#define   MASTER_CPLD_SYS_LED_RED                   (0x0c)
#define   MASTER_CPLD_FAN_LED_MASK                  (0x03)
#define   MASTER_CPLD_FAN_LED_OFF                   (0x00)
#define   MASTER_CPLD_FAN_LED_GREEN                 (0x01)
#define   MASTER_CPLD_FAN_LED_RED                   (0x02)

#define MASTER_CPLD_QSFP28_MUX_REG                  (0x1f | MASTER_CPLD_IDX)
#define   MASTER_CPLD_PORT_I2C_OE_MASK              (0xc0)
#define   MASTER_CPLD_PORT_I2C_OE_ENABLED           (0x00)
#define   MASTER_CPLD_PORT_I2C_OE_DISABLED          (0xc0)
#define   MASTER_CPLD_PORT_I2C_SEL_MASK             (0x3f)
#define   MASTER_CPLD_PORT_I2C_SEL_SHIFT            (0)

#endif  /* DELTA_AG9032V2_CPLD_H__ */
